1. Field of the Invention
The present invention relates to a method for manufacturing DRAM (Dynamic Random Access Memory) units, and relates in particular to a method for manufacturing a capacitor of a DRAM unit. More particularly, the present invention relates to a method which is capable of manufacturing a capacitor of a DRAM unit having an increased area.
2. Description of Prior Art
DRAMs have been widely used for a long time to temporally store data. Generally, a DRAM cell includes a MOS transistor 10 and a capacitor 12 as shown in FIG. 1. Further, the gate of the MOS transistor 10 is connected to the word line WL, and the drain and the source of the MOS transistor 10 are respectively connected to the bit line BL and grounded via the capacitor 12. However, the capacitor 12 should have a high capacitance to avoid a loss of data.
FIG. 2 schematically illustrates in cross-section a conventional DRAM cell, in which the reference number 2 represents the substrate; the reference number 20 represents the field oxide; the reference number 22 indicates the conductive lines; the reference number 24 represents the insulators; the reference number 30 represents the doped regions of the substrate, i.e., the source and the drain of the MOS transistor of the DRAM cell; the reference number 32 represents the gate of the MOS transistor; and the reference numbers 34, 36, 38 respectively represent the lower conductive layer, the dielectric layer and the upper conductive layer of the capacitor of the DRAM cell. The capacitance of the capacitor 12 is dependent on the dielectric constant, the thickness and the area of the dielectric layer. A larger area of the capacitor will result in a larger capacitance of the capacitor. However, as integrated circuits are fabricated with higher densities and smaller surfaces, this portion of the DRAM increasingly suffers from the drawback of a smaller capacitance.